Four years ago, as the semiconductor industry process technology crossed below 193 nanometers, the number of transistors available to a design team made it necessary to explore new design methods at a ...

Aiming to bring advanced verification languages like SystemVerilog and advanced methods like assertion-based verification to mainstream IC designers, Mentor Graphics this week is introducing its new ...

System Verilog is considered the current standard for a combined hardware description and verification language, and has been welcomed with open arms since it was approved by IEEE in 2005. Its ...

A sure sign that a design language is making its way into the mainstream is the appearance of a spate of tools supporting it. For SystemVerilog devotees, the latest good news is the commercial ...

Survey hardware design teams and you’ll find that the old saw is true: anywhere from 60% to 80% of the overall design cycle is consumed not with design itself, but rather with the nerve-wracking ...

FIFO (First In First Out) is a buffer that stores data in a way that data stored first comes out of the buffer first. Asynchronous FIFO is most widely used in the System-on-Chip (SoC) designs for data ...

Hundreds of variations of open-source CPUs written in an HDL seem to float around the internet these days (and that’s a great thing). Many are RISC-V, an open-source instruction set (ISA), and are ...